The present invention relates to a semiconductor device comprising MOSFETs having respective gate insulating films with different thicknesses and to a method of manufacturing the same.
As higher-speed operations have been achieved in recent semiconductor integrated circuit devices, the thickness of the gate insulating film of a MOSFET has been reduced increasingly.
On the other hand, a lower driving voltage has been pursued for a logic circuit in a semiconductor integrated circuit with the view to lowering the power consumption of the semiconductor integrated circuit device. In the peripheral circuit of the logic circuit for performing input/output operations, however, it is necessary to drive a MOSFET with a voltage inputted from the outside. To hold its breakdown voltage high, therefore, a transistor provided in the peripheral circuit of the logic circuit uses a gate insulating film having a larger thickness than a transistor provided in the internal circuit of the logic circuit.
A description will be given to a method of manufacturing MOSFETs having respective gate insulating films with different thicknesses.
First, as shown in FIG. 10(a), isolation region 11 are formed in a semiconductor substrate 10 made of silicon, followed by a first silicon oxide film 12a with a thickness of, e.g., 4 nm formed over the entire surface of the semiconductor substrate 10 to serve as agate insulating film. Thereafter, a resist pattern 13 is formed on the portion of the first silicon oxide film 12a corresponding to the peripheral circuit region of a logic circuit. Wet etching is then performed by using, e.g., hydrofluoric acid with respect to the first silicon oxide film 12a, thereby selectively removing the portion of the first silicon oxide film 12a corresponding to the internal circuit region of the logic circuit.
Next, as shown in FIG. 10(b), a second silicon oxide film 12b with a thickness of, e.g., 3 nm is formed over the entire surface of the semiconductor substrate 10.
Next, as shown in FIG. 10(c), a first gate insulating film 14A composed of the second silicon oxide film 12b and a first gate electrode 15A composed of a polysilicon film are formed in the internal circuit region of the logic circuit, while a second gate insulating film 14B composed of the first and second silicon oxide films 12a and 12b and a second gate electrode 15B composed of the polysilicon film are formed in the peripheral circuit region of the logic circuit.
Next, an impurity is implanted by using the first and second gate electrodes 15A and 15B as a mask to form lightly doped regions 16. Then, sidewalls 17 are formed on each of the first and second gate electrodes 15A and 15B. After that, an impurity is implanted by using, as a mask, the first and second gate electrodes 15A and 15B and the sidewalls to form heavily doped regions 18.
As a result, a first MOSFET including the first gate insulating film 14A composed of the second silicon oxide film 12b and having a thickness of 3 nm is obtained in the internal circuit region of the logic circuit, while a second MOSFET including the second gate insulating film 14B composed of the first and second silicon oxide films 12a and 12b and having a thickness of 7 nm is obtained in the peripheral circuit region of the logic circuit.
In accordance with the conventional method of manufacturing a semiconductor device, however, the second gate insulating film 14B obtained in the peripheral circuit of the logic circuit is formed in two separate steps, so that it is difficult for the second gate insulating film 14B to have a lifespan which is as long as the lifespan of a gate oxide film obtained in one oxidation step. This is because the second silicon oxide film 12b composing the second gate insulating film 14B is formed on the first silicon oxide film 12a after the resist pattern 13 is removed. Since the surface of the first silicon oxide film 12a has been contaminated or damaged in the step of removing the resist pattern 13, the reliability of the gate insulating film 14B is degraded.